Alif Semiconductor /AE722F80F55D5LS_CM55_HP_View /USB /GFLADJ

This bit field indicates the value that is used for frame length adjustment instead of considering from the sideband input signal FLADJ_30MHZ_REG. For details on how to set this value, refer to section , ‘Frame Length Adjustment Register (FLADJ),’ of the xHCI Specification.

This field selects whether to use the FLADJ_30MHZ_REG input signal or the GFLADJ[GFLADJ_30MHZ] to adjust the frame length for the SOF/ITP. When this bit is set to:

0 (Val_0x0): The controller uses the FLADJ_30MHZ_REG input signal value.

1 (Val_0x1): The controller uses the register field GFLADJ[GFLADJ_30MHZ] value.

This bit field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the REF_CLK. The GFLADJ_REFCLK_FLADJ value is used to adjust the ITP interval when the GCTL[SOFITPSYNC] bit is set to 0x1; SOF and ITP interval when the GFLADJ_REFCLK_LPM_SEL bit is set to 0x1. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL bit is set to 0x1. The value is derived as follows: FLADJ_REF_CLK_FLADJ = ((125000/REF_CLK_PERIOD_INTEGER) - (125000/REF_CLK_PERIOD)) x REF_CLK_PERIOD, where:

1. The REF_CLK_PERIOD_INTEGER is the integer value of the REF_CLK period got by truncating the decimal (fractional) value that is programmed in the GUCTL[REF_CLK_PERIOD] bit field.
2. The REF_CLK_PERIOD is the REF_CLK period including the fractional value.

• GUCTL[REF_CLK_PERIOD] = 41
• GFLADJ[GLADJ_REFCLK_FLADJ] = ((125000/41) - (125000/41.6666)) x 41.6666 = 2032 (ignoring the fractional value)
• GUCTL[REF_CLK_PERIOD] = 20
• GFLADJ[GLADJ_REFCLK_FLADJ] = ((125000/20) - (125000/20.8333)) x 20.8333 = 5208 (ignoring the fractional value)

This bit enables the functionality of running SOF/ITP counters on the REF_CLK. In Device mode, setting this bit to 0x1 enables SOF tracking using REF_CLK. Note that the REF_CLK frequencies supported in this mode are 16/17/19.2/20/24/39.7/40 MHz. Note: If this bit is set to 0x1, the GUSB2PHYCFG0[U2_FREECLK_EXISTS] bit must be set to 0x0.

This bit field indicates the decrement value that the controller applies for each REF_CLK in order to derive a frame timer in terms of a 240-MHz clock. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to 0x1. The value is derived as follows: GFLADJ_REFCLK_240MHZ_DECR = 240/REF_CLK_FREQUENCY Examples: If the REF_CLK is 24 MHz then:

• GUCTL[REF_CLK_PERIOD] = 41
• GFLADJ[GFLADJ_REFCLK_240MHZ_DECR] = 240/24 = 10
• GUCTL[REF_CLK_PERIOD] = 20
• GFLADJ[GFLADJ_REFCLK_240MHZ_DECR] = 240/48 = 5
• GUCTL[REF_CLK_PERIOD] = 58
• GFLADJ[GFLADJ_REFCLK_240MHZ_DECR] = 240/17 = 14

This bit indicates that the decrement value that the controller applies for each REF_CLK must be GFLADJ_REFCLK_240MHZ_DECR and GFLADJ_REFCLK_240MHZ_DECR + 1 alternatively on each REF_CLK. Set this bit to a 0x1 only if the GFLADJ_REFCLK_LPM_SEL bit is set to 0x0 and the fractional component of 240/REF_CLK_FREQUENCY is greater than or equal to 0.5. Examples: If the REF_CLK is 19.2 MHz then:

• GUCTL[REF_CLK_PERIOD] = 52
• GFLADJ[GFLADJ_REFCLK_240MHZ_DECR] = (240/19.2) = 12.5
• GFLADJ[GFLADJ_REFCLK_240MHZDECR_PLS1] = 1
• GUCTL[REF_CLK_PERIOD] = 41
• GFLADJ[GFLADJ_REFCLK_240MHZ_DECR] = (240/24) = 10
• GFLADJ[GFLADJ_REFCLK_240MHZDECR_PLS1] = 0